The present invention relates to a standard cell and a semiconductor device having a scan flip flop circuit for use in a system LSI (Large Scale Integrated circuit).
As the semiconductor technique develops, the number of logic circuits which can be mounted on a single semiconductor integrated circuit device is increasing dramatically. At present, one million or more logic circuits can be mounted on a common semiconductor integrated circuit device. It is therefore impossible to design the logic circuits one by one by a human. Such a semiconductor integrated circuit device is called a system LSI.
Therefore, a system LSI is designed on the basis of automatic designing using a computer with an EDA (Engineering Design Automation) tool. When the functions and architecture of a system are designed using an advanced function description language or the like, a logic synthesis tool automatically generates a logic circuit. An automatic placement and wiring tool converts the logic circuit to physical layout data. By using the physical data, LSIs can be mass-produced in a factory or the like.
Problems which become obvious as the scale of a logic circuit is becoming larger and a system LSI is designed automatically include a problem of designing of a test circuit and a problem of clock designing.
A test circuit is a circuit for determining a completed system LSI is accurately manufactured or not. Since a logic circuit in the system LSI is automatically designed, it is also difficult to manually design a test circuit for testing the logic circuit. Consequently, it is becoming natural to automatically design a test circuit.
As a method of testing a system LSI, a method called a scan test of using a test circuit in which a flip flop circuit (hereinbelow, abbreviated as FF circuit) in a system LSI is replaced with a scan flip flop circuit (hereinbelow, abbreviated as SFF circuit) is well known. For example, it is written specifically in FIGS. 12 to 20 of patent document 1.
A test circuit is automatically designated by replacing an FF circuit in a system LSI with an SFF circuit and coupling SFF circuits in order (scan path coupling) in a scan test.
As understood from FIG. 12 of the patent document 1, in the system LSI, logic circuits capable of realizing functions of the system LSI are arranged between logic circuits capable of storing data like FF circuits. Consequently, many FF circuits exist in a single system LSI. It is very important to supply the same clock signal, that is, clock signals which change to “1” or “0” at the same timing to the FF circuits. From the viewpoint of designing a system LSI, it is an important task to reduce a deviation (called clock skew) of timings at which the clock signals change in arbitrary two FF circuits.
When a clock skew exists, a hold error that an erroneous output of a logic circuit is stored in an FF circuit occurs. In this case, even if the cycle of the clock signal is delayed, the system LSI does not operate accurately.
100,000 or more SFF circuits are used in a system LSI at present. It is impossible to prevent a hold error in all of the SFF circuit statistically. Consequently, when a clock skew exists after generation of final layout, it has to be eliminated. To correct an erroneous part, a new buffer circuit is inserted or a wiring path is changed. It may cause a hold error in other SFF circuits. Usually, the correction cannot be made easily.
In the case of using a scan test, an SFF circuit has a configuration having an FF circuit and a 2-input selection circuit arranged before the FF circuit. Since the 2-input selection circuit is added for a test, the number of logic stages increases.
When the number of logic stages increases, a signal delay of the amount occurs. The signal delay is a big issue in the data communication field.
In the data communication field, a convolution code or the like is often used for restoring communication information influenced by noise or the like in a communication path on the reception side. Generally, Viterbi decoding is used as a method of restoring a convolution code, and a main logic circuit of the Viterbi decoding is called an ACS circuit.
The ACS circuit stands for “Add, Compare, and Select”, and is comprised of, as the name suggests, an adder, a comparator, and a selector.
In the above-described scan test, the ACS circuit corresponds to a logic circuit between SFF circuits. In this case, the selector existing in the SFF circuit cannot be ignored as a delay element. Consequently, in a system LSI having the ACS circuit, the SFF circuit cannot be used, and a scan test cannot be employed.
[Patent Document 1]
Japanese Unexamined Patent Publication No. 2002-267723 (FIGS. 12 to 20)